AXI Multi-Channel DMA Capable SPI Master and Slave controller IP

Green Electrons Multi-Channel SPI controller with integrated DMA engine, allows the user to easily have up to 16 independent concurrent Master or Slave SPI interfaces.

Key facts and contents

• One single IP handles up to 16 cuncurrent SPI channels.

• The IP is capable of performing DMA to DRAM memory to fetch the data which should be sent over any of SPI interfaces or to put the data received from any of SPI interface in the memory.

• Software can configure the IP and then stand aside completely while the Multi-Channel SPI controller is operating.

• Multi-Chanel SPI controller can also be configured at the time of instantiation in the design. The IP becomes fully operational the soonest FPGA comes up and without any need for any configuration from CPU. This is particularly useful in scenarios where the SPI interface should be active before any software running on CPU cores executing.

Synplified symbolic representation

The following Figure shows a symbolic representation of the IP.

Target FPGA families

IP is compatible with AMD Zynq, Zynq Ultrascale+, and all other Series-7 devices.

Support

The package comes with email based support. During your learning and using the IP, whenever you have questions or doubts about the IP or any of the provided examples, you simply write us an email and it will be answered as soon as possible.

Pricing

If you are a student then there exists a 10% discount on the above prices for you.

Licensing

The license of the package asks the customer (individual, company or research lab) to pay attention that the entire provided content is for customer's own personal educational use only.

Questions?

Might you have any questions, please kindly look at the contacts menu and write me an email. It will be answered as soon as possible.