Green-Electrons This Green-Electrons IP provides a very easy-to-use, low-area-utilization solution for FPGA interfacing to AD1937 and AD1939 Audio CODECs.
IP contains integrated IIC and SPI interfaces so it can configure AD1937 and AD1939 based on selected options by the user just after reset.
The integrated IIC and SPI engines bring several advantages:
- User does not need to develop any code for configuring of AD1937/AD1939. He/she only sets desired parameters when instantiating the IP in Vivado and those will be programmed into the device by IP after reset.
- The IP and AD1937/AD1939 become fully operational just immediately after FPGA comes up. User does not need to wait for software or the OS on CPUs to come up to configure AD1937/AD1939.
- User does not need to instantiate a separate AXI IIC or AXI SPI controller IP, saving FPGA resources.
- In the advanced version of AD1937/AD1939 Interface IP the software can talk to the IP through an AXI slave interface can change the AD1937/AD1939 configuration at run-time.
A symbolic representation of the IP when connected to AD1937 is shown in the following:
A symbolic representation of the IP when connected to AD1939 is shown in the following:
As can be seen in the Figures:
- The IIC interface of the IP can be used for configuring the AD1937 device and the SPI interface to configure AD1939.
- AD1937/AD1939 IF is the ensemble of signals between AD1937/AD1939 and FPGA for transferring data sample bits. The IP contains all of the interface definitions as well.
- There are 4 AXI stream slave interfaces through which the data for DACs flows into the IP. The data will then gets passed to the AD1937/AD1939.
- There are 2 AXI stream master interfaces as well. Digitized audio samples received from AD1937/AD1939 will be passed to the next on-FPGA module thourgh these axi stream interfaces.
In addition to above, here are more key points about the IP:
- For both of ADC and DAC interfaces, sampling rates of 48KHz, 96KHz and 192KHz are supported by the IP.
- Also, the IP supports sample data width of 16Bits, 20Bita and 24Bits for both of ADCs and DACs.
- Each of the AXI stream interfaces of the IP can operate in a different clock domain.
- There is an aditional debug interface provided by the IP which can directly get connected to a system ILA for further monitoring of IP's behavior.
The following Figure shows the IP instantiated in Vivado block design along with the GUI to customize IP parameters.
- Operatio mode can be: iic, spi, Master and Slave. User can select between any of these four options and the IP performs required IO settings to put the AD1937/AD1939 device in that mode.
- ADC and DAC sampling rates can be any of 48KHz, 96KHz or 192KHz. ADC and DAC can have different sampling rates. The IP will configure AD1937/AD1939 based on the choice of the user.
- Bits per sample can be any of 24, 20 or 16 Bits. ADC and DAC can have different sample width values.
- AXI stream interfaces of the IP can have any of 16, 24 or 32 Bits width. This can be set for ADC axi stream interfaces and DAC axi stream interfaces separetly. Interface width should always be bigger or equal to sample width.
- All produced and received numbers on the interfaces of the IP are 2's complement. IP performs required sign extension automatically when stream interface is wider then sample width.
- The IP can produce TLAST signal along with the outgoing samples over the AXI stream master interfaces. User can select how often the TLAST should be produced.
- When using AD1937 at iic mode, user can select the chip address. For AD1939 which operates in spi mode, chip address has no effect.
- User can revert the DAC output if needed.
- The IP contains an internal VIO which shows the values programmed into AD1937/AD1939 registers at the time of bringup. This VIO can be enabled or disabled by the user.
AD1937/AD1939 Interface IP Vivado Design Examples
Many Vivado design examples for Xilinx targets are provided along with the IP. Here is the list of examples and their related information.
- Example 1: Shows the basic usage and connectivity of AD1937/AD1939 IP. (Example 1 block design)
Supported FPGAs and Validation of the IP
Currently the IP supports Xilinx FPGA targets. The IP is tested on ZYNQ 7000 SoCs with Analog Devices evaluation board for AD1939 and a custom built board for AD1937.
In the following you can see photos and snapshots from the test setup and on-board tests done on the IP.
- A photo of test setup using AD1939 evaluation board and z-turn ZYNQ 7000 board. AD1937/AD1939 Interface IP configures the AD1939 device through the SPI and sends DAC data to AD1939 and receive ADC data from it through ADC and DAC interface signals. (Photo here)
- Comparison of catured signal on the audio outputs of the board using Oscilloscope and sample values entering the IP through DAC AXI stream interface. (Photo here).
- Debug interface of AD1937/AD1939 IP provides the user with the possibility of looking into behavior of the interface by reflecting key signals of the IP. Here we see bit clock and frame clock signals when AD1939 is configured at 192 KHz sampling rate. (Photo here)
- The IP contains an internal VIO which reflects the programmed value of registers to user. This VIO can be enabled with IP parameters when instantiating the IP. User can see the programmed values of AD1937/AD1939 chip registers using this VIO to make sure all IP parameters are applied correctly to the chip. (Photo here)
Pricing
| Index | Package content | Price (euros) |
|---|---|---|
| 1 | AD1937/AD1939 Interface IP package, containing RTL source code for the IP along with example design and videos that describe the IP and each of example designs in detail. | 490 |
| 2 | Item number 1 plus design examples including Ai based speech recognition using DPU IP core and speech generation. | 2490 |
Payment through any of direct bank account transfer and Paypal is possible.
Licensing
The license of the package asks the customer (individual, company or research lab) to pay attention that the entire provided content is for customer's own personal educational use only.
Support
The IP comes with Green Electrons support. Might you have any questions, or doubts during using the IP for your project, you can simply write an email and Green Electrons makes sure your doubt or issue gets solved.
Questions
Might you have any questions regarding the IP, please kindly have a look at the Contacts page and write Green Electrons an E-mail. It will be responded immediately.