AXI DRAM to Block memory Bridge IP

This IP allows you to easily transfer data between any of PL or PS side DRAM memory and block memories in your FPGA design.

This is useful for example when another component (e.g. CPU) has written some data into DRAM memory and now you want to read back that data and feed it into your FPGA modules.

The reverse is also true. Sometimes you want the data that your module has written into a block memory, gets transferred to DRAM so that it can be read from there by other on-chip components.

Also, sometimes you may like to share the data between FPGA modules using the DRAM memory.

This IP allows you to do all of these tasks easily and very fast.

DRAM BRAM Bridge symbolic representation

Key facts

It should be noted that the M_AXI interface of the IP can get connected to a PS-side AXI HP slave port as well.

Consequently, the PS-side DRAM memory can be shared for storing and retrival of data as well.

The IP provides an AXI slave plug through which the CPU (software) can configure the IP.

CPU can indicate the addresses in DRAM memory to which the IP should store the data from block memories and also the DRAM addresses from which the IP should read the data and write back to block memories.

These addresses however, can also be indicated with FPGA logic through the dedicated address ports.

This allows the hardware to act completely independent of the software whenever needed.

The following Figure shows a simplified design block diagram in which the IP is connected to ZYNQ PS.

The following Figure shows a simplified design in which the IP is operating without any software present. In this case an on-FPGA module is responsible for giving the read and write addresses to the bridge IP.

In this example Module 1 produces data and writes it into BRAM memory. Module 2 grabs the data from BRAM memory and performs calculations on it.

The scheduler module gives the bridge IP the address and data transfer length values and also triggers each of the DRAM write (from Module 1 BRAM) and DRAM read (to Module 2 BRAM) operations.

The following Figure shows the configuration GUI of the IP in Vivado. Through this interface user can define number of BRAM memories which should be connected to the IP, data width values, and if the IP should be configured and triggered through software or directly by its ports.

The following Figure shows the IP symbol when 8 of BRAM interfaces are enabled and the IP will be configured and trigger by the software.

DRAM BRAM Bridge and Vitis HLS IPs

AXI DRAM BRAM bridge IP is very suitable for communicating with IPs produced by Vivado HLS or Vitis HLS, These IPs use BRAM-like interface by default.

AXI DRAM BRAM bridge can be used to transfer data between DRAM and BRAM memories which then will be accessed by Vitis HLS generated IPs.

Three complete design examples are included in the package to demostrate this. Deisngs contain Vitis HLS IPs, Vivado project which shows how AXI DRAM BRAM bridge can be used in such designs to transfer data to and from Vitis HLS generated IP, and the software which runs on the CPU Cores (in the PS).

Here is the list of 3 IPs included:

• A Vitis HLS IP which reads the numbers from BRAM memory and calculates the average. A Vivado design which uses AXI DRAM BRAM bridge to transfer data from DRAM memory to this IP.

• A Vitis HLS IP which reads a set of numbers (from BRAM memory) and calculates sine or cosine for each number and writes back the result ao another location in the BRAM memory.

• A Vitis HLS IP which calculate a FIR filter output on the data series in the BRAM.

Using the mentioned IPs and AXI DRAM BRAM bridge, the following Vivado design examples (along with their related software) are available in the package:

• Vivado design example which transfers floating point arrays from DRAM memory to BRAM and calculates their average.

• A software controlled, function generator to produce sine, cosine, rectangular analog waveforms with amplitude of up to 20 volts. Interface IP to Texas Instrument's DAC61402 (DACx1402) is added to this design example. Vitis HLS generated IP is used to calculate the function.

• Vivado design example for performing signal processing (filtering) in FPGA using Vitis HLS generated IP.

Package contents

• Verilog RTL for AXI DRAM-BRAM Bridge IP, along with simulation testbenches.

• Packaged IP and related tcl scripts

• Example vivado design which shows how to configure and use the IP without the need for software. (Sharing data between FPGA modules over DRAM.)

• Example vivado design shows how to share data between software (CPU) and on FPGA module over the DRAM.

• Example vivado design shows how to use Vitis HLS generated IPs in our design easily with the help fo AXI DRAM BRAM bridge.

• Linux kernel level driver and user level application to show how to configure the IP via software. (can be used with PetaLinux)

• Linux kernel level driver and user level application to demonstrate data sharing between software and on-FPGA modules using the DRAM-BRAM bridge. (can be used with PetaLinux)

• Videos describing the operation of the IP, example designs, drivers and performing on-board tests.

• Support, answering all questions that you might have realted to IP.

Target FPGA families

The package is mainly intended to be used for AMD (Xilinx) ZYNQ, ZYNQ Ultrascale+ or similar devices.

Pricing

If you are a student, there will be a 10% discount on the above value for you.

Licensing

The license allows the buyer to use the IP and package contents for his/her own personal (institute, group) use.

Questions?

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