AXI DRAM FIFO

This Green-Electrons IP provides a FIFO (like any other FIFO in our FPGA designs) with a difference that the FIFO uses DRAM memory as its storage.

The following shows a symbolic representation of the IP and how it gets connected to the rest of the system.

 

Symbolic representation of AXI DRAM FIFO Interface IP

 

The following shows again the symbolic representation of the IP and its connection to the ZYNQ PS.

 

Another symbolic representation of AXI DRAM FIFO Interface IP