PCI Express connectivity using Xilinx XDMA IP


This Practical Educational Package is a guide for building PCI Express connections between your FPGA card and the PC. Xilinx XDMA IP is used for this purpose. Topics related to design architecture, board bringup, PCIe link validation, basic linux kernel level driver for the PCIe device are covered.


Register based data read/write operation between PCIe device (FPGA card) and PC (Host) is discussed in detail.


DMA operation for transfering data from the Host DRAM memory to FPGA card DRAM memory, and from FPGA card DRAM memory to host DRAM memory are discussed in detail with fully working design example.


DMA operations for tranfering (AXI) stream of data from FPGA card to Host DRAM memory, and from Host DRAM memory to an AXI stream of data on the FPGA is addressed in detail with working design example.


Methods to improve the data transfer bandwidth (descriptor bypass and handling buffers) are studied with design examples in the package.

 

Key facts and contents

Package contains Vivado designs, source codes for Linux kernel level driver, source codes for user level application and descriptive videos on created designs and the written source codes.


Package contains several complete design examples (FPGA Vivado design, FPGA side code, PC Host side driver and user level application) covering all data transfer scenarios between Host and FPGA.


Any FPGA target that supports XDMA IP can be used with this package. The designs are tested on ZCU106 and ZCU111 boards.

 

List of videos in the package

Here is a list of videos included in the package along with their description:


  • PCIe connectivity folder structure: description of contents of the package

  • Vivado project: How to instantiate, connect and configure XDMA IP for PCIe connectivity

  • Vitis project and BOOT.BIN generation: goes through the process of creating a vitis project and BOOT.BIN file containing FPGA bitstream

  • Booting from QSPI flash: procedure and required configuration for programming the QSPI flash with BOOT.BIN and booting the board from QSPI.

  • Review of key points: goes through key points one need to check to have a working PCIe link

  • Evaluating the working PCIe link: checking PCIe device presence and its properties at PC side.

  • In-system eye scan: goes through the steps required and process of performing in-system statistical eye scan for each PCIe link.

  • PC side Linux kernel level driver (part A): describes the structure of the linux kernel level driver, building and using the driver, the initilization process.

  • PC side Linux kernel level driver (part B): describes driver's device struct, file operations, io controls implementation

  • PC side Linux kernel level driver (part C): describes the probe function and its implementation

  • User level application: describes the PC side user level application which uses the driver to perform read and write operations.

  • On-board tests: practical tests and design validation using ZCU106 board.

  • Introduction to Host DRAM to FPGA DRAM direct memory access (DMA) over PCIe using XDMA

  • Vivado design for DRAM to DRAM DMA over PCIe using XDMA

  • Description of DMA operation process and descriptors, example software code for user level application

  • Studying linux kernel level driver IO controls

  • Memory allocation and managing addresses in Linux kernel level driver

  • Creating descriptors for XDMA Card-to-Host and Host-to-Card data transfers

  • Controlling DMA channels in Linux kernel level driver

  • Studying host DRAM to AXI stream (and vice versa) DMA data transfer over PCIe, Vivado project

  • Linux kernel level driver for FPGA-side AXI stream to host DRAM (and vice versa) DMA operations

 

Support

Package comes with full e-mail based support. Whatever question you might have during your learning, or whatever problem you face, you can simply write an email and Green Electrons will make sure the doubt, issue and request will be addressed. There is no time limitation for this support.

 

Pricing

Total price for PCIe package with register based data transfer (peripheral IO) is 240 euros.

Total price for PCIe package with register based data transfer, Host DRAM to FPGA DRAM DMA transfer and FPGA DRAM to Host DRAM DMA transfer is 490 euros.

Total price for PCIe package containing above items plus Host to FPGA stream DMA transfer and FPGA stream to Host DRAM data transfer is 590 euros.

Complete package, including all above items, plus topics of link speed improvement and Descriptor Bypass is 690 euros.

 

License

Package is provided for educational use of the individual, company or institute who has purchased the package. The customer is asked to avoid distibuting or sharing the package content with others.

 

Contact

Might you have any question regarding the package, please write us an email. It will be answered as soon as possible.