RGMII to AXI stream bridge IP

Many times there are multiple Gigabit Ethernet PHYs connected to FPGA programmblae fabirc (Programmable logic)(PL) and we need to receive Ethernet packets from the PHY and send our generated packets back to it. The RGMII to AXI stream bridge IP is a suitable choice for these scenarios.

For example you have several ADCs connected to your PL (FPGA) and you would like to send the ADC data as UDP packets over the network to a host PC. With the help of RGMII to AXI stream IP you can achive this in a very short time and without any need for CPU or software intervention. Furthermore, imagine you would like to receive Ethernet packets over RGMII interface, perform some statistical analysis on the packets and forward them back or drop them or transmit them over another medium. For all these cases RGMII to AXI stream bridge IP can be directly used.

If you have a hardware board in which (due to mistake in PCB design or lack of pins) a dedicated clock capable FPGA pin is not used for RX clock from RGMII, the RGMII to AXI stream IP can still operate fine. RGMII to AXI stream IP implements two types of data capture mechanism inside, allowing it to capture data fine even if RXC is not located at a clock capable pin.

RGMII to AXI stream IP contains integrated MDIO engine. It can perform any sequence of MDIO register read and writes for getting the PHY status and for configuring the PHY easily and quickly. Again the IP can operate in pure hardware mode without any need for the software, or when user wants, the IP provides an AXI slave interface through which user can access the MDIO registers.

Symbolic representation

Key facts and contents

• Package contains RTL source code for the IP along with several design examples. Designs and scripts are compatible with Vivado 2020.2.

• Package comes with customization support, meaning that if you have a board with a special RGMII PHY on it, I provide you an update on the MDIO interface and sequence of commands for configuration of the PHY.

• Package can be used for any FPGA target. Validation of the IP is done on Xilinx Zynq Ultrascale+ platform. (xczu7ev device)

• RGMII to AXI stream IP contains integrated CRC check and calculation engines on both TX and RX sides.

• The complete IP with all featured enabled consumed around 1K LUTs, 2k FFs and 3 BRAM18s.

• The RX interface of the IP supports two modes 1) direct sampling: in this mode RXC (RX clock) signal coming from PHY is just one of the signals entering FPGA like others. In this mode RXC does not need to be connected to a clock capable pin. 2) rxc capture: in this mode RXC signal will be used as the clock inside FPGA to capture the incoming data and control signals. In this mode MDIO interface configures the PHY to add proper skew to RX clock so that the capture of data happens in the middle of the window.

• Package comes with videos that describe the IP and its usage as well as example designs.

In the following, you can see the configuration GUI of the IP in vivado and also its representation in Vivado block design.

Documentation

Users guide for RGMII to AXI stream IP can be downloaded here.

Target FPGA families

The IP is compatible with AMD (Xilinx) Zynq, Zynq Ultrascale+, and all of Series-7 FPGAs.

Support

As described this package has customization support. Meaning that we will support you to (if needed) customize the IP (pogramming sequence of registers on the PHY) so that it works fine on your board. This will come at an additional cost.

IP has email based support. Might you have any questions or doubts regarding the IP, we are available to answer your questions or doubts through email.

Pricing

If you are a student then there is a 10% discount available for you.

License

The license of the package asks the customer to pay attention that the entire provided content is for his or her personal (institute, group) use only.

Questions?

Might you have any questions, please kindly look at the contacts menu and write me an email. It will be answered as soon as possible.