Timed AXI DMA: Scatter-Gather DMA engine with integrated scheduler


Green Electrons Timed AXI DMA IP is a very easy to use AXI DMA engine with Scatter-Gather capability and integrated timers. This allows the user to perform S2MM (stream to memory) or MM2S (memory to stream) data transfers within exact time intervals without any need for attention from software. This makes the IP a suitable choice for real-time data transfer tasks.


IP can be used with any Series-7 AMD (Xilinx) device (Zynq, Zynq Ultrascale+, Kintex, Artix, Spartan,...)


 

Key facts and contents


  • Two IPs are provided, one for S2MM and another for MM2S data transfers.

  • Timed AXI DMA IP is a very easy to use Scatter-Gather DMA engine. Software can program the transfers that the IP should do in the beginning, software then starts the IP operation. Timed AXI DMA will operate without any need for software attention since then.

  • Programming the data transfer tasks (known as descriptors) into the IP is very easy and straight forward. Allocated memory buffers for data transfers in DRAM do not need to be equal sized or continous.

  • IP contains integrated timers, software can program the interval at which data transfer should happen into the IP. Once running, the IP will perform the data transfers at programmed interval.

  • Package contains Timed AXI DMA IP RTL source code and all necessary related tcl scripts

  • Package contains numerous examples showing how to use the IP in diferent setups.

  • Package contains example software showing usage of the IP in standalone (baremetal) mode.

  • Package contains Linux kernel level driver and numerous Linux user level applications showing how to use the IP under Linux.

  • Provided Linux examples cover both PetaLinux and Ubuntu for Zynq and Zynq Ultrascale+ devices.

  • Provided software examples demostrate how to use the IP along with transferring data over the network. Examples cover both cases where the FPGA board is a Host allowing network clients to connect for data transfer, as well as when the FPGA board is a network client connecting to a Host PC. All examples show how network data transfer and DMA transfer tasks can be combined and synchronized.

  • Package contains Video recordings describing the design of the IP, the RTL source code, scripts, Linux kernel level driver, and each of user level applications in detail.


 

Support

The package comes with email based support. During your learning and using the IP, whenever you have questions or doubts about the IP or any of the provided examples, you simply write us an email and it will be answered as soon as possible.


 

Pricing

Index Package content Price (euros)
1 Timed AXI DMA IP (MM2S) RTL, Linux kernel level driver, example standalone and Linux user level application covering using the DMA engine along with network data transfer. 990
2 Timed AXI DMA IP (S2MM) RTL, Linux kernel level driver, example standalone and Linux user level application covering using the DMA engine along with network data transfer. 990
3 Complete items 1 and 2 together. 1790
 

If you are a student then there exists a 10% discount on the above prices for you.

 

Licensing

The license of the package asks the customer (individual, company or research lab) to pay attention that the entire provided content is for customer's own personal educational use only.

 

Questions?

Might you have any questions, please kindly look at the contacts menu and write me an email. It will be answered as soon as possible.