AXI interfaces, Hardware-software data sharing, Petalinux and Linux kernel level driver development


This Practical Educational Package is a complete course on AXI interfaces and using them in designs. Its main focus is on ZYNQ and ZYQN ultrascale+ devices, the concepts however can be used for any device with AXI interfaces.

The course is available in two forms:


  • With in person training, recorded videos, example designs, and support

  • With recorded videos, example designs and support


During the in person training, the focus can be on the contents of the course directly, or it can be more on any topic that you find more useful for your project.

The course comes with 100+ recorded videos covering the following areas:


  • AXI stream interfaces

  • AXI memory mapped interfaces

  • Designing with Vivado

  • Using visit environment

  • Zynq and Zynq Ultrascale+ PS AXI interfaces, Cache-coherent interface

  • Using Petalinux

  • Driver development under Linux

Details for each part comes in the following.


Session 1: AXI stream interfaces

  • Importance of interfaces and their role in creating designs

  • More about ARM AXI Interfaces

  • Running vivado in Linux and Windows

  • Vivado design example: Data sharing between Microblaze CPU and XDMA PCIe IP

  • Further description of Microblaze and XDMA data sharing example: Address ranges and interrupts

  • Vivado design example: ADC interface and signal processing using FFT and FIR filter IPs plus storage of results in PL side DRAM

  • Creating Vivado tcl scripts to automate design creation and to improve design version management

  • Vivado design example: ADC data capture and transferring data over the network using UDP packets (pure FPGA based solution).

  • Vivado design example: Using Xilinx deep learning unit IP (brief)

  • Other types of interfaces than AXI

  • Creating a simple AXI stream interface

  • RTL coding of simple AXI stream slave and master interfaces

  • Packaging an IP in Vivado

  • Vivado design example: Using Virtual IO (VIO), System ILA and Clocking Wizard in designs, dealing with differential clock inputs

  • Brief overview of Pin Assignment process in Vivado

  • When to use our RTL as a packaged IP in Vivado block design, when to instantiate it as a module

  • Example AXI stream design, evaluation on ZCU106 board

  • Further description of System ILA and using it

  • The role of TREADY, TLAST, TUSER AXI stream signals

  • Using AXI stream FIFOs in designs, using Asynchronous AXI stream FIFOs

  • Example AXI stream master module with TREADY and TUSER present

  • Example AXI stream master module which acts as a Video Frames generator

  • Example Vivado design with AXI Video DMA

  • Debugging our AXI Video Frames generator IP using System ILA

  • Differences between AXI DMA and AXI VDMA IPs

  • Further description of System ILA operation and the role of trigger position


Session 2: AXI memory mapped interfaces

  • Description of AXI memory mapped Lite interface and read transaction on this interface

  • Describing AXI write transactions in an AXI Lite interface

  • Further clarification of AXI Bus

  • Read FSM in an AXI Lite interface

  • AXI Lite vs. AXI Full memory mapped interfaces

  • RTL coding of an AXI Lite master

  • Packaging AXI master Lite IP

  • An example Vivado project using AXI Master Lite IP

  • Assigning addresses to AXI slaves, further description of addresses in a block design

  • Further describing register space of an IP with AXI MM lite interface

  • More about addresses in block design

  • Using Vivado connection automation

  • On-board test of our example Vivado design

  • Vivado example design: using PL side DRAM memory

  • Describing read and write response channels in AXI memory mapped interfaces

  • PS DRAM vs. PL DRAM

  • Using PS side and PL side DRAMs concurrently

  • Adding Microblaze CPU to our Vivado design

  • More about XSA files

  • Vitis environment, creating a project in Vitis

  • Developing software for Microblaze

  • Further description of UART interfaces and Vitis software libraries

  • More about ELF files

  • On-board test of example design: Sharing data between Microblaze and AXI Lite master over PL side DRAM memory

  • Design example: Performing DMA from PL to PS DRAM using AXI DMA IP

  • Description of PS components, address ranges, Real-time processing unit, Application processing unit and PS interfaces

  • Further details on PS AXI interfaces

  • Further description of PS AXI coherent interfaces

  • Creating and using IPs with AXI Lite slave interface

  • Example software (C code) for accessing AXI lite slave (from Microblaze)

  • On-board test of example design


Session 3: Petalinux

  • Initial steps for setting up a Petalinux project

  • Folder structure and compoents of a Petalinux project

  • Discussion on Linux bringup process and steps happening during booting

  • Dealing with Petalinux build failures

  • Using board support packages for Petalinux projects

  • Discussion on advantages and disadvantages of using BSPs in Petalinux projects

  • Petalinux build process outputs

  • Exploring the device tree, device tree structure, device tree blobs

  • Device tree aliases, device tree kernel parameters

  • Creating boot images (in Petalinux)

  • Creating boot images using Vitis

  • First Petalinux on-board bringup

  • More talks abour UART connection from FPGA board to PC

  • Comparing device trees between projects

  • Customizing a device tree

  • Using SSH in Petalinux

  • Further discussion of ssh and scp commands

  • RAMDISK vs. permanent root file systems

  • Customizing root file system in Petalinux: adding HTTP server and I2C tools

  • On-board test of Petalinux based HTTP server

  • Customizing the Linux kernel

  • User level applications vs. kernel level drivers

  • Using devmem for direct access to IO and memory space

  • First Petalinux example user level app, using mmap to access hardware registers of FPGA modules

  • Physical addresses vs. virtual addresses, more description of MMU operation

  • More about devmem

  • More about PL only designs in ZYNQ

  • Programming QSPI flash


Session 4: Linux kernel level driver development

  • Creating a simple Linux kernel level driver (in Petalinux)

  • Further description about our simple Linux kernel level driver

  • Driver: registering a platform device, device match structure and role of compatible string

  • Driver probe and remove subroutines

  • Answering questions on device tree customization and driver's platform device structure

  • On-board test of our first driver, using lsmod, insmod, modprobe and further discussion

  • Implementation of driver's probe subroutine: getting platform resources, requesting memory, performing IO remapping

  • Using FPGA manager, PL configuration after Linux bringup

  • FPGA manager and device tree overlays

  • PL reconfiguration with different bitstreams and different devicetrees

  • Petalinux is for Microblaze too

  • On-board test: PL reconfiguration

  • Registering a character device in a Linux kernel level driver

  • Defining file operations in a Linux kernel level driver

  • Implementation of IO controls in a Linux kernel level driver

  • Looking at AXI DMA in register mode vs. AXI DMA in scatter-gather mode

  • Further discussion on implementation of IO controls in a Linux kernel level driver

  • Implementation of mmap in a Linux kernel level driver

  • Interrupt service routines in a Linux kernel level driver

  • Further discussion on Alveo cards and ASIC emulation

 

Pricing

Index Package content Price (euros)
1 Session 1 only. 90
2 Session 2 only. 120
3 Session 3 only. 180
4 Session 4 only. 190
5 All sessions together. 490

If you are a student you will have 10% discount over the above prives.

 

Licensing

The provided content in the package shall be used for educational use of the purchasing person/entity (company or research lab) only.