Designing with AXI Multi-Channel DMA with Scatter-Gather data transfer and using it under Linux

This package shows you how to use AXI Multi-channel DMA in Vivado and how to use it under Linux. It also shows how to use AXI DMA in SG mode. It shows how to create and use descriptors and how to perform descriptor based data transfers.

The package comes with an additional IP: AXI MCDMA Scheduler. The IP can feed up to 16 AXI stream interfaces into AXI MCDMA. The IP supports different stream width values for each of the streams. The IP supports different DMA transfer sizes for each of the streams. The IP supports handling of different packet sizes over each stream.

The package contains currently 4 design examples. Each design includes Vivado design, Linux kernel level driver and user level application. These are ready and tested and I can deliver it to you right now. All of the examples use the DMA in SG mode.

The package mainly targets Xilinx ZYNQ and ZYNQ Ultrascale+ devices. It however can be used for any Xilinx FPGA device.

Here is the introduction video of this package. (Watch on youtube)

Note: If you are interested in using AXI DMA in Scatter-Gather mode, please also have a look at AXI DMA package.

Design Examples

In the following you can download the block diagram of the design examples included into the package. Each design example comes with its Linux kernel level driver and user level application.

• Design example 1: one PL to PS stream with AXI MCDMA in Scatter-Gather mode.
• Design example 2: four PL to PS streams with AXI MCDMA in SG mode. Streams are in a same clock domain.
• Design example 3: four PL to PS streams with AXI MCDMA SG. Streams are in different clock domain, have different data width, packet size and data rate.
• Design example 4: one PL to PS stream with AXI MCDMA in Scatter-Gather mode running the transfer forever (ring buffer mode)(infinite transfer).

List of available videos

Here is the list of available videos for the package. Each of the videos are by average 20 minutes long.

• mcdma_sg_pl_to_ps_part_1_folders_structure : goes through folder structure of the package. Describes the purpose of each folder and steps for packaging the mcdma scheduler IP, creating design examples and petalinux project.
• mcdma_sg_pl_to_ps_part_2_section_A : describes the principles of operation of AXI MCDMA IP, and its differences with normal AXI DMA IP.
• mcdma_sg_pl_to_ps_part_2_section_B : describes the interfaces of AXI MCDMA IP and their role and operation.
• mcdma_sg_pl_to_ps_part_2_section_C : describes the register space of AXI MCDMA IP. Meaning of registers, their operation and programming flow of registers.
• mcdma_sg_pl_to_ps_part_2_section_D : describes the role of descriptors in performing DMA operations. Talks about how descriptors should be used and how they will be consumed and updated by AXI MCDMA IP.
• mcdma_sg_pl_to_ps_part_3_mcdma_scheduler_ip : Details AXI MCDMA Scheduler IP, its architecture and capabilities. Talks about how this IP can multiplex up to 16 AXI streams into one AXI MCDMA IP.
• mcdma_sg_pl_to_ps_part_4_vivado_designs : Goes through provided Vivado design examples in the package and describes each design and related ideas in detail.
• mcdma_sg_pl_to_ps_part_5_devicetree_customization : Talks about using devicetree generator in Vitis environment and customization of devicetree in Petalinux to allow our kernel level driver to manage AXI MCDMA IP.
• mcdma_sg_pl_to_ps_part_6_kernel_driver_section_A : Investigates the linux kernel level driver structure, probe and file operations
• mcdma_sg_pl_to_ps_part_6_kernel_driver_section_B : Investigates the implementation of device IO controls in our Linux kernel level driver for AXI MCDMA IP.
• mcdma_sg_pl_to_ps_part_6_kernel_driver_section_C : Continues looking at the implementation of device IO controls in our Linux kernel level driver.
• mcdma_sg_pl_to_ps_part_7_user_app_onboard_test : Goes through the user level application code written for the first design example. Further describes the interaction between user level application and kernel level driver. Performs an on-board test of the design. Investigates the bahvior of AXI MCDMA IP using System ILA.

Support

Might you purchase the package along with in-person training (for any number of hours you see necessary), I will be available to answer any of your questions and concerns in our online meeting calls. Furtheremore, after the calls I am still available to answer any of your questions through email.

Might you be interested in Source Code plus Video version of the package, I am available to answer your questions or doubts through email.

In the above I have assumed you already have ordered the AXI DMA package and you have used it and you are familiar with the concepts of AXI DMA and driver development for it.

Pricing

The price for the package is 390 euros. It is strongly suggested that you first learn through AXI DMA package and then this package.

For package with in-person training please contact me. If you are a student then there exists a 10% discount on the above price for you.

Licensing

The license of the package asks the customer (individual, company or research lab) to pay attention that the entire provided content is for customer's personal educational use only.

Questions?

Might you have any questions, please kindly look at the contacts menu and write me an email. It will be answered as soon as possible.